1. Field of the Invention
The present invention relates to a dual bit nonvolatile programmable read/write memory, a method of manufacturing the same, and a method of driving the same.
2. Description of the Prior Art
In the flash memory, the limit of miniaturization is decided by limits in the reduction in the voltages, the cell area, and the electrostatic capacity scaling. In contrast, the realization of the multivalue operation per one element is expected as the element technology to meet the trend of cost reduction.
Also, there is the memory like the mask ROM, which does not need the reprogramming, among the nonvolatile memories and it is desired to supply the product at a low price. In this case, the realization of the multivalue operation per one element is also watched with interest as the element technology to meet the lower cost.
Under such circumstances, the structure of the nonvolatile memory that makes it possible to realize the multivalue operation per one element is disclosed in the U.S. Patent (U.S. Pat. No. 6,011,725).
According to this Patent, the localization of the trapped charge by the MONOS (Metal Oxide Nitride Oxide Semiconductor) structure is utilized to obtain the 2-bit 4-value states. This system is the unique system that utilizes the event that the threshold value of the device can be decided by the fixed charges located locally near the source region and also the source region and the drain region are exchanged in operation, so that 2-bit (i.e., 4-value states) data can be generated by one transistor.
In FIG. 1A and FIG. 1B of this application, the similar element structure to that of the above U.S. Patent is shown. More particularly, the source/drain regions 6a, 6b serving as the source or the drain are formed at a distance on the surface of the one conductivity type semiconductor substrate 1, and the ONO (Oxide Nitride Oxide) structure in which the nitride film 3 is sandwiched by oxide films 2, 4 is formed on the channel region between them, and the control gate 5 is formed on the ONO structure. The overall stacked structure constitutes the MONOS structure.
In the programming of data, the avalanche breakdown is caused in the pn junction, that consists of the source/drain region 6a or 6b and the semiconductor substrate 1, by applying the program voltage to the source/drain region 6a or 6b to generate hot electrons. The electrons are injected into the ONO structure near the pn junction, and then trapped by the electron trap in the nitride film 3. At this time, normally the trapped electrons are located locally in the nitride film 3 near the pn junction.
FIG. 1B shows the state that the accumulated charges (trapped electrons) 7a and 7b are located locally in vicinity of the source/drain regions 6a and 6b respectively when the program voltage (Vpp) is applied separately to the source/drain regions 6a and 6b respectively. This state shows one state of the 2-bit 4-value states.
In the reading of this data, the current in one direction is detected while using the source/drain region 6a as the source and the source/drain region 6b as the drain, and then conversely the current in the opposite direction is detected while using the source/drain region 6b as the source and the source/drain region 6a as the drain. In both cases, since the accumulated charges 7a or 7b exist on the source side and thus the electric field to turn off the channel is generated, the detected current is small to indicate the xe2x80x9cOFFxe2x80x9d state.
However, problems described in the following still remain in the above nonvolatile memory.
(i) Programming Control
In the programming, as described above, normally the trapped electrons are located locally near the pn junction. However, there is the possibility that the trapped electron distribution in the nitride film is expanded by the excessive programming. In this case, since asymmetry of the operation is lost because the localization of the trapped electrons cannot be implemented, it is impossible to execute the dual bit operation. In order to prevent such excessive programming, the precise control of the programming time is needed.
Also, even if the precise control of the programming time can be carried out, the channel length must be set long to some extent in view of the expansion of the trapped electron distribution in the nitride film to locate locally the charges on both sides of the nitride film at the same time. Therefore, it may be concluded that the structure in the prior art is not suitable for the higher density achieved by the miniaturization.
(ii) Variation in the Threshold Value
Since the avalanche breakdown is caused locally, it is difficult to localize the fixed charged uniformly over the overall area along the channel width direction shown in FIG. 1A.
It is an object of the present invention to provide a semiconductor memory device which has high reliability and makes it possible to achieve miniaturization and a higher density, and each element of which is operated at multi-values.
It is another object of the present invention to provide a semiconductor memory device capable of achieving lower voltages in a programming voltage and much more expanding a current window defined later.
It is still another object of the present invention to provide a method of manufacturing the above semiconductor memory device.
It is yet still another object of the present invention to provide a method of driving the above semiconductor memory device.
The gist of the inventions set forth in claims will be explained hereunder. In this case, some portions will be explained with reference to the drawings. This intends to explain contents of the invention comprehensively, but this does not intend to limit the scope of the invention.
A semiconductor memory device set forth in claim 1 of the present invention containing a semiconductor memory element, the element comprises a one conductivity type semiconductor substrate in which convex portions having a pair of opposing side surfaces is provided, a pair of opposite conductivity type source/drain regions formed on a surface of the semiconductor substrate on both sides of the convex portion, a first insulating film for covering upper surface of the convex portion, second insulating films for covering the side surfaces of the convex portion and the source/drain regions, a pair of floating gates provided on the sides surfaces of the convex portions to oppose to the side surfaces and the source/drain regions via the second insulating film respectively, third insulating films formed on the floating gates, and control gate opposing to the upper surface of the convex portion via the first insulating film and opposing to the floating gates via the third insulating films respectively.
In this case, as set forth in claim 2, a region neighboring to the side surfaces and upper surface of the convex portion put between a pair of the source/drain regions acts as a channel region, and a pair of floating gates act as charge accumulating regions for accumulating charges.
In the present invention, two bits are formed per one element by a pair of the floating gates, and 4-value states can be formed by possible combinations of the charge accumulation or no charge accumulation into the one floating gate and the charge accumulation or no charge accumulation into the other floating gate.
Also, since the floating gates are provided on both side surfaces of the convex portion formed on the surface of the semiconductor substrate and also side surfaces of the convex portion are utilized as a channel respectively, a element forming area can be reduced. Also, since the source/drain regions are provided under the floating gates, the higher density of the semiconductor memory device can be achieved.
In the programming, hot carriers (high energy carriers) generated by the electric field directed from the source to the drain are employed as the injection charge. At this time, the energy required for the hot carriers to exceed the energy barrier of the gate insulating film is supplied by applying the necessary voltage for programming to the drain. More particularly, as shown in FIG. 6, the carriers extracted from the source are accelerated during the traveling in the channel region to get the energy, and then exceeds the energy barrier of the gate insulating film 22 to jump into the floating gate 27b. At this time, since the floating gate 27b is present in the acceleration direction of the carriers in the channel on the upper surface of the convex portion, the carriers are injected into the floating gate 27b as they are without the change of direction. Accordingly, the energy of the carriers accelerated in a direction of the floating gate 27b is never lost by scattering and is practically used as the energy to exceed the energy barrier of the gate insulating film 22 as they are. Therefore, according to the present invention, it is possible to execute the programming by the low voltage.
Also, since a pair of floating gates as the charge accumulating portions are separately mutually to put the convex portion between them, in the programming, the charges injected into the floating gates do not interfere mutually, and thus contents of the data can be clearly distinguished. In addition, since the floating gates are formed of the conductor, the injected hot carriers (charges) can be distributed uniformly in the floating gates. Accordingly, xe2x80x9cONxe2x80x9d/xe2x80x9cOFFxe2x80x9d of the transistors can be controlled perfectly.
Further, during the programming, in the non-selected cell transistor, 0 V is applied to the control gate and the source, and the programming voltage is applied to the drain, but the potential of the floating gates is pulled up to the drain potential by the coupling capacitance between the drain and the floating gate. Therefore, the potential difference between the drain and the floating gate is reduced. As a result, the dielectric breakdown due to the inter-band tunneling, etc. that are caused by the high electric field to the insulating film between the drain and the floating gate can be prevented.
In addition, since the floating gates are provided on the source/drain regions via the insulating film, the potential of the floating gate is largely affected by the drain voltage via the coupling capacitance. Accordingly, since the potential of the floating gate is pulled up by the drain voltage even if the injected electrons are accumulated in the floating gate on the drain side, a drain current can be increased.
In contrast, the potential of the floating gate on the source side is pulled down by the source voltage applied to the source via the coupling capacitance of the insulating film between the floating gate and the source. Therefore, the potential of the floating gate that is pulled down by the injected electrons into the floating gate on the source side is further pulled down by the source voltage. As a result, even if the high voltage is applied to the control gate, the channel can be still cut off.
The pulling-up of the potential of the floating gate by the above drain voltage and the pulling-down of the potential of the floating gate by the source voltage can generate the effect to increase the so-called xe2x80x9ccurrent windowxe2x80x9d. Here, the current window is the index of the margin in a discrimination of xe2x80x9cONxe2x80x9d state and xe2x80x9cOFFxe2x80x9d state. In other words, it is a difference between the lowest level of the drain current indicating the xe2x80x9cONxe2x80x9d state and the highest level of the drain current indicating the xe2x80x9cOFFxe2x80x9d state. More particularly, it is corresponding to the difference between the drain current values obtained when the voltages are applied in different directions between the drain and the source of the memory element in which xe2x80x9c1xe2x80x9d is programmed onto one floating gate only.
Also, in the semiconductor memory device set forth in claims 4 to 9, a plurality of semiconductor elements are arranged in columns and rows.
In claim 4, the semiconductor convex portions in which the memory elements are formed at intersecting regions of the rows and the columns are arranged like the islands to implement the element isolation such that the mutual interference between neighboring memory elements is not generated.
While, in claims 5 to 9, a plurality of memory elements are formed on the stripe-shaped convex portions. In this manner, in case the memory elements are left discontinuously at a distance in the stripe-shaped convex portion in one column, high concentration impurity regions (element isolation layers) are formed between neighboring memory elements to accomplish isolation between the elements without fail.
In the semiconductor memory device driving method of the present invention, the programming of the data, the reading of the stored data, and the erasing of the programmed and stored data can be carried out as follows.
The programming of the data is carried out in the following way. That is, the voltage is applied to at least any one of a pair of the source/drain regions 23a, 23b, for example, the source/drain region 23b in FIG. 6. And then, the high-energy carriers that can exceed the energy barrier of the insulating film 22 are generated in the electric field which is built in the peripheral region of the source/drain region 23a, 23b and the channel region, to inject and accumulate the charges in the floating gate 27b. 
Also, as shown in FIG. 7A to FIG. 7D, the reading of the stored data is carried out to pass drain currents through a transistor while exchanging a source and drain of the transistor and to detect the drain currents.
More particularly, in case that the source/drain region 23a or 23b on the side of the floating gate 27a or 27b in which the charges are accumulated is used as the source, the accumulated charges produce the potential to turn off the channel. In addition, since a potential of the floating gate 27a or 27b is pulled down by the high coupling capacitance between the floating gate and the source to lower its potential, the drain current can be easily cut off by a small amount of the accumulated charges.
In contrast, in case the source/drain region 23a or 23b on the side of the floating gate 27a or 27b in which the charges are accumulated is used as the drain, a potential of the floating gate 27a or 27b is pulled up by the high coupling capacitance to increase its potential close to the drain voltage. Therefore, even if the accumulated charges are present in the floating gate 27a or 27b, the influence on the drain current is small and thus the current value is not so reduced.
As shown in FIG. 7D, in the case that the accumulated charges are present in both the floating gates 27a and 27b, the drain current is brought into the cut-off state on the basis of the above operation in either case if any one of the floating gates 27a and 27b is set to the source side or the drain side. Because the accumulated charges are present in the floating gate 27a or 27b of the source side in either case.
Also, as shown in FIG. 7B and FIG. 7C, in case that the accumulated charges are present in any one of the floating gates 27a and 27b, the drain current is brought into the cut-off state when the floating gate 27a or 27b in which the charges are accumulated is set to the source side, but the drain current flows when the floating gate 27a or 27b in which the charges are accumulated is set to the drain side. In other words, the drain current flows or not depending on the direction of the voltage that is applied between the source and the drain.
In addition, as shown in FIG. 7A, if the charges are accumulated in neither the floating gate 27a nor 27b, the potential of the floating gate 27a or 27b is increased by the gate voltage applied to the control gate 30a. For this reason, the xe2x80x9cONxe2x80x9d state of the channel is maintained, and thus the drain current still flows even if the direction of the applied voltage between the source and the drain is changed.
In this manner, if the voltages are applied while the source and the drain are exchanged and then the currents passing through the transistor are detected, it is possible to detect four different states.
Further, since the floating gates and the source/drain regions are overlapped with each other, it is possible to exhaust the charges accumulated in the floating gates into the source/drain regions in erasing the stored data.
Besides, in the semiconductor memory device manufacturing method set forth in claim 10, the convex portions each having a pair of opposing side surfaces are formed, and then the opposite conductivity type impurities are introduced into a surface layer of the semiconductor substrate on both sides of the convex portion such that two source/drain regions are formed on both sides of the convex portion to put the convex portion between them. In addition, a pair of floating gates are formed on the side surfaces of the stripe-shaped convex portion via the insulating film (second insulating film) by anisotropic-etching the first conductive film.
In this manner, according to the semiconductor memory device manufacturing method, since the source/drain regions and the floating gates can be formed in a self-alignment manner, further miniaturization can be achieved.
Moreover, as shown in FIG. 10H, the thick insulating films 34 are formed in the regions which are located on the common source/drain regions 23a, 23b between the convex portions 24a, 24b and in which the source/drain regions 23a, 23b oppose to the control gates 30a, 30b formed later. As a result, the dielectric-breakdown resistance of the semiconductor memory device can be improved.